1. Technical Field
This disclosure relates to integrated circuits, and more particularly, to exiting low power states of integrated circuits.
2. Description of the Related Art
Managing power consumption in integrated circuits (ICs) such as computer system processors and various types of system-on-a-chip (SoC) ICs is increasingly important. This is true not only during times when an IC is actively performing work, but also during times when the IC is idle. In particular, the small feature sizes of transistors in ICs can result in leakage currents and thus power consumption even in functional units that are otherwise not performing any work.
When a functional unit of an IC becomes idle, power management hardware or software may take various actions to reduce power consumption. Reducing clock frequencies or gating clocks may reduce dynamic power consumption. Reducing a supply voltage may provide additional reductions in power consumption. In some cases, a functional unit may be power gated (i.e. may have power removed therefrom) when it is idle. This may be referred to as a deep sleep state.
Entry into a low power or sleep state may be accomplished by performing various actions. Consider for example an SoC having multiple processor cores and a power management unit implemented thereon. Actions performed in placing a processor core into a sleep state may include flushing any caches that will lose power, turning off power from phase locked loops (PLLs), saving system states, and so forth. Upon entry into the low power or sleep state, the processor core may remain there until an external interrupt or other action that causes initiation of a wakeup of the core.